ECET-230 – Digital Circuits and Systems week four iLab

ECET-230 – Digital Circuits and Systems week four iLab


Laboratory Report Cover Sheet
DeVry University
College of Engineering and Information Sciences




Course Number: ECET-230

Professor:

Laboratory Number: 4

Laboratory Title:Introduction to Flip-Flops

Submittal Date:Click here to enter a date.



Objectives:

•          To simulate the operation of a circuit used to create an edge-triggered D flip-flop.

•         To test the operation of a 74LS74 D flip-flop

•         To test the operation of a 74LS112 J-K flip-flop



Program:



•         To simulate the operation of a circuit used to create an edge-triggered D flip-flop.





Questions:





1.      Why is the condition when both and are LOW considered illegal?


1.      How does the value you measured for tsetupcompare with value specified in the 74LS74 data sheet? You may need to go on-line to find this value.

Why were the LEDs removed before making the propagation delay measurements

Modify the VHDL Architecture for the 74LS112 J-K flip-flop so that the preset (PRE) is synchronous instead of asynchronous. The clear (CLR) remains asynchronous.

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